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Centre for Microsystems Engineering

Centre for Microsystems Engineering - Publications


Prof Andrew Richardson
Andrew Richardson

Journals, Books and Book Chapters

2009

  1. "Guest Editorial: Mixed-Technology Testing; Rapid System Prototyping"
    Marcelo Lubaszewski, Andrew Richardson & C.C. Su
    Microelectronics Journal, Special Issue, Volume 40, Issue 7, July 2009, Page 1041
    doi:10.1016/j.mejo.2008.11.058

2008

  1. "Online Testing of MEMS based on Encoded Stimulus Superposition"
    N. Dumas, Z. Xu, K. Georgopoulos, R. J. T. Bunyan & A. Richardson
    Springer Journal of Electronic Testing, Volume 24, Number 6, December 2008, pp555-566
    doi:10.1007/s10836-008-5090-2, ISSN 1573-0727
  2. "A Dependable Micro-Electronic Peptide Synthesizer Using Electrode Data"
    H. G. Kerkhoff, Z. Xu, F. Mailly, P. Nouet, H. Liu & A. Richardson
    VLSI Design Volume 2008 (Accepted 23rd May 2008), Article ID 437879, 9 pages.
    doi:10.1155/2008/437879
  3. "Phase Locked Loop Test Methodologies"
    M. J. Burbidge & A. Richardson
    Book Chapter in: Test & Diagnostics of Analogue, Mixed Signal & RF Integrated Circuits, IET Press, May 2008, pp277-307
    ISBN 978-0-86341-745-0
  4. "Test of A/D Converters"
    A. Lechner & A. Richardson
    Book Chapter in: Test & Diagnostics of Analogue, Mixed Signal & RF Integrated Circuits, IET Press, May 2008, pp213-234
    ISBN 978-0-86341-745-0

Conference and Workshop Papers

2010

  1. "Design and simulation of a multi-function MEMS sensor for health and usage monitoring"
    Xu, Z.; Koltsov, D.; Richardson, A.; Le, L. & Begbie, M.
    Proceedings of the IEEE Prognostics and Health Management Conference, 12th-14th January 2010
    doi:10.1109/PHM.2010.5413415, ISBN: 978-1-4244-4756-5

2009

  1. "Integrated Sensors for Health Monitoring in Advanced Electronic Systems"
    C. H. Wang, Y. Liu & A. Richardson
    Invited paper: 4th IEEE International Design and Test Workshop (IDT09), Riyadh, 15th - 17th Nov 2009
  2. "Built-in Test Solutions for the Electrode Structures in Bio-Fluidic Microsystems"
    Q. Al-Gayem, H. Liu, A. Richardson & N. Burd
    Proceedings of the 2009 European Test Symposium, 25th-29th May 2009, pp. 73-78,
    doi:10.1109/ETS.2009.24, ISSN 1530-1877 , ISBN 978-0-7695-3703-0
  3. "Health Monitoring of Aircraft Wiring by Acoustic Method"
    Saha, S. Xu, Z. Koltsov, D. Richardson, A. & Sutherland, A
    IEEE Aerospace Conference, 7-14 March 2009, pp. 1-10,
    doi:10.1109/AERO.2009.4839677

2008

  1. "Embedded Health Monitoring Strategies for Aircraft Wiring Systems"
    Z. Xu, S. Saha, D. Koltsov, A. Richardson, B. Honary, A. Sutherland, J. Hannu & M. Desmulliez
    Proceedings of the IEEE Electronic Systems Technology Conference, 1st-4th Sept. 2008, pp427-433
    doi:10.1109/ESTC.2008.4684392, ISBN: 978-1-4244-2813-7
  2. "Embedded Test & Health Monitoring Strategies for Bio-Fluidic Microystems"
    H. Liu, A Richardson, T Harvey, T Ryan & C Pickering
    Proceedings of the IEEE Electronic Systems Technology Conference, 1st-4th Sept. 2008, pp463-469
    doi:10.1109/ESTC.2008.4684386, ISBN: 978-1-4244-2813-7
  3. "Failure Mechanisms of Legacy Aircraft Wiring and Interconnects"
    B.G. Moffat, E. Abraham, M.P.Y Desmulliez, D. Koltsov & A. Richardson
    IEEE Transactions in Dielectric and Electrical Insulation, Vol. 15, No. 3, June 2008, pp. 808-822
    doi:10.1109/TDEI.2008.4543119, ISSN: 1070-9878
  4. "Dissipation in MEMS in the near-vacuum regime"
    R. Rosing, D. Liu, A. Ghisi & A. Richardson
    Proceedings of the 8th World Congress on Computational Mechanics (WCCM8), Venice, Italy, June 30th - July 5th, 2008
  5. "Acoustic System for Online Wiring Test on Aircraft"
    Z. Xu, D. Koltsov, S. Saha, A. Richardson & A. Sutherland
    Proceedings of the 14th IEEE International Mixed-Signals Testing Workshop (IMSTW), Vancouver, 18th - 20th June 2008
    doi:10.1109/IMS3TW.2008.4581601, ISBN: 978-1-4244-2395-8
  6. "Delivering Bio-Mems & Microfluidic Education Around Accessible Technologies"
    A. Richardson, H. Liu, D. Koltsov, R. Rosing, T. Ryan & R. Wootton
    Proceedings of the 8th European Workshop on Microelectronics Education, Budapest, May 28th - 30th 2008
    EDA Publishing, ISBN: 978-2-35500-007-2
  7. "Model based design optimization of micro mechanical systems, based on the Cosserat theory"
    T. Wiegand, D. Peters, R. Laur, A. Richardson, R. Rosing, M. Del Sarto & L. Baldo
    Proceedings of Optimization of Electrical and Electronic Equipment (OPTIM), 22nd-24th May 2008, pp33-38
    doi:10.1109/OPTIM.2008.4602340, ISBN: 978-1-4244-1544-1
  8. "An Embedded Test & Health Monitoring Strategy for Detecting and Locating Faults in Aerospace Bus Systems"
    Jari Hannu, Denis Koltsov, Zhou Xu, Andrew Richardson and Markku Moilanen
    Proceedings of the IEEE European Test Symposium, Italy 25th-29th May 2008

Invited Talks

2010

  1. "Overview of PanEuropean Packaging Activities & Initiatives"
    Prof. Andrew Richardson, Lancaster University
    Packaging and Integration Challenges for Micro & Nano Enabled Sensors, Nanotechnology KTN event, 21st January 2010
    https://ktn.innovateuk.org/web/nanoktn/document-library

2009

  1. "Embedded Reliability & Test Engineering in MEMS Enabled Systems"
    Prof. Andrew Richardson, Lancaster University and Prof. Nihal Sinnadurai, ATTAC
    IEEE CPMT/Reliability Society outreach Seminar & Workshop, University of Greenwich, 14th-15th September 2009
    http://reliability-outreach.gre.ac.uk/
  2. "MEMS for Structural Health Monitoring - Challenges for the Test Community"
    Prof. Andrew Richardson, Lancaster University
    Invited mini-tutorial: 15th IEEE Mixed Signal, Sensors and Systems Test Workshop (IMS3TW), Scotsdale, Arizona, 10th-12th June 2009
    http://www.lirmm.fr/~w3mic/IMS3TW09/program.htm

2008

  1. "Enhancing Reliability and Testability in Micro and Nanosystems through Systems Design, Modelling and Simulation"
    Prof. Andrew Richardson, Lancaster University
    MEMS Metrology: An Update, National Physical Laboratory (NPL), 11th December 2008
    http://resource.npl.co.uk/docs/networks/mnt/20081211_mems_flyer.pdf
  2. "Delivering Bio-MEMS & MicroFluidic Education around Accessible Technologies"
    Prof. Andrew Richardson, Lancaster University, Dr Tim Ryan, Epigem, Dr Rob Wootton, Liverpool John Moores University
    Second STIMESI Workshop on MEMS and Microsystems Research and Teaching, Berlin-Brandenburg Academy of Sciences and Humanities, Germany, 18th November 2008
    http://www.stimesi.org/WS2Program_and_presentations.html
  3. "Design for Manufacture Challenges in MEMS enabled Micro & Nano Systems"
    Prof. Andrew Richardson, Lancaster University
    ESSCIRC tutorial, Lancaster University, 15th September 2008
    http://essderc.iop.org/Integrating%20CMOS%20with%20other%20Technologies.pdf
  4. "Disruption & Emerging Challenges"
    Prof. Andrew Richardson, Lancaster University
    Nanotech, iKNOW European Project Meeting
    http://wiwe.iknowfutures.eu/

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Dr Dinesh Pamunuwa
Dinesh Pamunuwa

Journal Articles

2009

  1. "Two-Dimensional and Three-Dimensional Integration of Heterogeneous Electronic Systems under Cost, Performance and Technological Constraints" R. Weerasekera, D. Pamunuwa, L-R. Zheng & H. Tenhunen
    IEEE Transactions on Computer-Aided Design, Volume: 28, Issue: 8, August 2009, pp1237-1250
    doi:10.1109/TCAD.2009.2021734, ISSN:0278-0070

2008

  1. "Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime"
    R. Weerasekera, D. Pamunuwa, L-R. Zheng & H. Tenhunen
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume: 16, Issue: 5th May 2008, pp589-593
    doi:10.1109/TVLSI.2008.917555, ISSN:1063-8210

Conference and Workshop Papers

2010

  1. "On Signalling Over Through-Silicon Via (TSV) Interconnects in 3-D Integrated Circuits"
    R. Weerasekera, M. Grange, D. Pamunuwa, & H. Tenhunen
    Proceedings of the Design Automation and Test in Europe (DATE) Conference, Dresden, Germany, 8th - 12th March 2010
    www.date-conference.com/proceedings

2009

  1. "Design of Robust Molecular Electronic Circuits"
    C. Lei, D. Pamunuwa, S.Bailey & C. Lambert
    IEEE International Symposium on Circuits and Systems (ISCAS) 2009, Taipei, Taiwan, 24th - 27th May 2009, pp1819 - 1822
    doi:10.1109/ISCAS.2009.5118131, ISBN:978-1-4244-3827-3
  2. "Physical Mapping and Performance Study of a Multi-Clock 3-Dimensional Network-on-Chip Mesh"
    M. Grange, A. Y. Weldezion, D. Pamunuwa, R. Weerasekera, Z. Lu, A. Jantsch & D. Shippen
    Proc. IEEE International Conference on 3D System Integration (3D IC), San Francisco, USA, 28th-30th September 2009
    doi:10.1109/3DIC.2009.5306540, ISBN:978-1-4244-4511-0
  3. "Compact Modelling of Through-Silicon Vias (TSVs) in Three-Dimensional (3-D) Integrated Circuits"
    R. Weerasekera, M. Grange, D. Pamunuwa, H. Tenhunen, & L-R. Zheng
    Proc. IEEE International Conference on 3D System Integration (3D IC), San Francisco, USA, 28th-30th September 2009
    doi:10.1109/3DIC.2009.5306541, ISBN:978-1-4244-4511-0
  4. "Scalability of the Network-on-Chip communication architecture for 3-D meshes"
    A. Y. Weldezion, M. Grange, D. Pamunuwa, Z. Lu, A. Jantsch, R. Weerasekera, & H. Tenhunen
    Proc. ACM/IEEE International Symposium on Networks on Chip (NOCS), San Diego, USA, 2009, pp114-123
    doi:10.1109/NOCS.2009.5071459, ISBN:978-1-4244-4142-6
  5. "Designing Reliable Digital Molecular Electronic Circuits"
    C. Lei, D. Pamunuwa, S. Bailey, & C. Lambert
    Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, Volume 20, Part 1 (Proc. Third International Conference on Nano-Networks (Nanonet)), Lucerne, Switzerland, 18th-20th October 2009, pp111-115
    doi:10.1007/978-3-642-04850-0_17, ISSN:1867-8211, ISBN:978-3-642-04849-4
  6. "Closed-Form Equations for Through-Silicon Via (TSV) Parasitics in 3-D Integrated Circuits (ICs)"
    R. Weerasekera, D. Pamunuwa, M. Grange, H. Tenhunen, & L-R. Zheng
    Workshop Notes, Design, Automation and Test in Europe (DATE), Nice, France, 2009
    Lancaster University ePrints: 31106
  7. "Examination of Delay and Signal Integrity Metrics in Through Silicon Vias"
    M. Grange, R. Weerasekera, D. Pamunuwa, & H. Tenhunen
    Workshop Notes, Design, Automation and Test in Europe (DATE), Nice, France, 2009
    http://www.ipack.kth.se/ELITE/publications/DATE_Workshop_2009
  8. "Bandwidth Optimization for Through Silicon Via (TSV) Bundles in 3D Integrated Circuits"
    M. Grange, R. Weerasekera, D. Pamunuwa, & H. Tenhunen
    Workshop Notes, Design, Automation and Test in Europe (DATE), Nice, France, 2009
    Lancaster University ePrints: 31108

2008

  1. "Application of Molecular Electronics Devices in Digital Circuit Design"
    C. Lei, D. Pamunuwa, S.Bailey and C. Lambert
    Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering (Proc. Third International Conference on Nano-Networks (Nanonet)), Boston, USA, 14th-16th September 2008, pp61-65
    doi:10.1007/978-3-642-02427-6, ISSN: 1867-8211, ISBN: 978-3-642-02426-9
  2. "Memory Technology for Extended Large-Scale Integration in Future Electronics Applications"
    D. Pamunuwa
    Proc. Design, Automation and Test in Europe (DATE) Conference, Hot Topic Session, Munich, Germany, 10th-14th March 2008, pp1126-1127
    doi:10.1109/DATE.2008.4484828, ISBN: 978-3-9810801-3-1

Invited Talks

2008

  1. "The Memory Challenge in NoC Based Systems"
    D. Pamunuwa, R. Weerasekera & A. Richardson
    Proc. Design, Automation and Test in Europe Conference (DATE), Hot Topic Session, Munich, Germany, 10th-14th March 2008
    ISBN: 978-3-9810801-3-1

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Dr Roshan Weerasekera
Roshan Weerakesera

Journal Articles

2009

  1. "Two-Dimensional and Three-Dimensional Integration of Heterogeneous Electronic Systems under Cost, Performance and Technological Constraints" R. Weerasekera, D. Pamunuwa, L-R. Zheng & H. Tenhunen
    IEEE Transactions on Computer-Aided Design, Volume: 28, Issue: 8, August 2009, pp1237-1250
    doi:10.1109/TCAD.2009.2021734, ISSN:0278-0070

2008

  1. "Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime"
    R. Weerasekera, D. Pamunuwa, L-R. Zheng & H. Tenhunen
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume: 16, Issue: 5th May 2008, pp589-593
    doi:10.1109/TVLSI.2008.917555, ISSN:1063-8210

Conference and Workshop Papers

2010

  1. "On Signalling Over Through-Silicon Via (TSV) Interconnects in 3-D Integrated Circuits"
    R. Weerasekera, M. Grange, D. Pamunuwa, & H. Tenhunen
    Proceedings of the Design Automation and Test in Europe (DATE) Conference, Dresden, Germany, 8th - 12th March 2010
    www.date-conference.com/proceedings

2009

  1. "3-D Memory Organization and Performance Analysis for Multi-processor Network-On-Chip Architecture"
    Awet Yemane Weldezion, Zhonghai Lu, Roshan Weerasekera, & Hannu Tenhunen
    Proc. IEEE International Conference on 3D System Integration (3D IC), 2009, San Francico, USA, 28th-30th September 2009
    doi:10.1109/3DIC.2009.5306593, ISBN:978-1-4244-4511-0
  2. "Physical Mapping and Performance Study of a Multi-Clock 3-Dimensional Network-on-Chip Mesh"
    M. Grange, A. Y. Weldezion, D. Pamunuwa, R. Weerasekera, Z. Lu, A. Jantsch & D. Shippen
    Proc. IEEE International Conference on 3D System Integration (3D IC), San Francisco, USA, 28th-30th September 2009
    doi:10.1109/3DIC.2009.5306540, ISBN:978-1-4244-4511-0
  3. "Compact Modelling of Through-Silicon Vias (TSVs) in Three-Dimensional (3-D) Integrated Circuits"
    R. Weerasekera, M. Grange, D. Pamunuwa, H. Tenhunen, & L-R. Zheng
    Proc. IEEE International Conference on 3D System Integration (3D IC), San Francisco, USA, 28th-30th September 2009
    doi:10.1109/3DIC.2009.5306541, ISBN:978-1-4244-4511-0
  4. "Scalability of the Network-on-Chip communication architecture for 3-D meshes"
    A. Y. Weldezion, M. Grange, D. Pamunuwa, Z. Lu, A. Jantsch, R. Weerasekera, & H. Tenhunen
    Proc. ACM/IEEE International Symposium on Networks on Chip (NOCS), San Diego, USA, 10th-13th May 2009, pp114-123
    doi:10.1109/NOCS.2009.5071429, ISBN:978-1-4244-4142-6
  5. "Design of Network-On-Chip Communication Architecture for 3-D multiprocessor Systems-On-Chip"
    A. Y. Weldezion, M. Grange, D. Pamunuwa, Z. Lu, A. Jantsch, R. Weerasekera, & H. Tenhunen
    Proc. ACM/IEEE International Symposium on Networks on Chip (NOCS), San Diego, USA, 10th-13th May 2009, pp114-123
    doi:10.1109/NOCS.2009.5071429, ISBN: 978-1-4244-4142-6
  6. "Closed-Form Equations for Through-Silicon Via (TSV) Parasitics in 3-D Integrated Circuits (ICs)"
    R. Weerasekera, D. Pamunuwa, M. Grange, H. Tenhunen, & L-R. Zheng
    Workshop Notes, Design, Automation and Test in Europe (DATE), Nice, France, 20th-24th April 2009
    Lancaster University ePrints: 31106
  7. "Examination of Delay and Signal Integrity Metrics in Through Silicon Vias"
    M. Grange, R. Weerasekera, D. Pamunuwa, & H. Tenhunen
    Workshop Notes, Design, Automation and Test in Europe (DATE), Nice, France, 20th-24th April 2009
    http://www.ipack.kth.se/ELITE/publications/DATE_Workshop_2009
  8. "Bandwidth Optimization for Through Silicon Via (TSV) Bundles in 3D Integrated Circuits"
    M. Grange, R. Weerasekera, D. Pamunuwa, & H. Tenhunen
    Workshop Notes, Design, Automation and Test in Europe (DATE), Nice, France, 20th-24th April 2009
    Lancaster University ePrints: 31108
  9. "Power Integrity Issues in 3-D Integrated Chips Using TSVs (Through Silicon Vias)"
    Waqar Ahamd, Qiang Chen, Roshan Weerasekera, Hannu Tenhunen & Li-Rong Zheng
    3D Integration Workshop, The Design, Automation, and Test in Europe (DATE), Nice, France, 20th-24th April 2009
    http://www.ipack.kth.se/ELITE/publications/DATE_Workshop_2009

2008

  1. "High Frequency Characterization and Modeling of Inkjet Printed Coplanar Strips on Flexible Substrate"
    Botao Shao, Roshan Weerasekera, Abraham Tareke Woldegiorgis, Li-Rong Zheng, Ran Liu, & Werner Zapka
    Proceedings of the 2nd Electronics System-Integration Technology Conference, Greenwich, London, 1st-4th September 2008, pp695-699
    doi:10.1109/ESTC.2008.4684435, ISBN: 978-1-4244-2813-7
  2. "High Frequency Characterization of Inkjet Printed Coplanar Waveguides"
    Botao Shao, Roshan Weerasekera, Li-Rong Zheng, Ran Liu,Werner Zapka, & Peter Lindberg
    12th IEEE Workshop on Signal Propagation on Interconnects, Avignon, France, 12th-15th May, 2008, pp1-4
    doi:10.1109/SPI.2008.4558383, ISBN: 978-1-4244-2317-0

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Matt Grange
Matt Grange

Conference and Workshop Papers

2010

  1. "On Signalling Over Through-Silicon Via (TSV) Interconnects in 3-D Integrated Circuits"
    R. Weerasekera, M. Grange, D. Pamunuwa, & H. Tenhunen
    Proceedings of the Design Automation and Test in Europe (DATE) Conference, Dresden, Germany, 8th - 12th March 2010
    www.date-conference.com/proceedings

2009

  1. "Physical Mapping and Performance Study of a Multi-Clock 3-Dimensional Network-on-Chip Mesh"
    M. Grange, A. Y. Weldezion, D. Pamunuwa, R. Weerasekera, Z. Lu, A. Jantsch & D. Shippen
    Proc. IEEE International Conference on 3D System Integration (3D IC), San Francisco, USA, 28th-30th September 2009
    doi:10.1109/3DIC.2009.5306540, ISBN:978-1-4244-4511-0
  2. "Compact Modelling of Through-Silicon Vias (TSVs) in Three-Dimensional (3-D) Integrated Circuits"
    R. Weerasekera, M. Grange, D. Pamunuwa, H. Tenhunen, & L-R. Zheng
    Proc. IEEE International Conference on 3D System Integration (3D IC), San Francisco, USA, 28th-30th September 2009
    doi:10.1109/3DIC.2009.5306541, ISBN:978-1-4244-4511-0
  3. "Scalability of the Network-on-Chip communication architecture for 3-D meshes"
    A. Y. Weldezion, M. Grange, D. Pamunuwa, Z. Lu, A. Jantsch, R. Weerasekera, & H. Tenhunen
    Proc. ACM/IEEE International Symposium on Networks on Chip (NOCS), San Diego, USA, 10th-13th May 2009, pp114-123
    doi:10.1109/NOCS.2009.5071429, ISBN:978-1-4244-4142-6
  4. "Closed-Form Equations for Through-Silicon Via (TSV) Parasitics in 3-D Integrated Circuits (ICs)"
    R. Weerasekera, D. Pamunuwa, M. Grange, H. Tenhunen, & L-R. Zheng
    Workshop Notes, Design, Automation and Test in Europe (DATE), Nice, France, 20th-24th April 2009
    Lancaster University ePrints: 31106
  5. "Examination of Delay and Signal Integrity Metrics in Through Silicon Vias"
    M. Grange, R. Weerasekera, D. Pamunuwa, & H. Tenhunen
    Workshop Notes, Design, Automation and Test in Europe (DATE), Nice, France, 20th-24th April 2009
    http://www.ipack.kth.se/ELITE/publications/DATE_Workshop_2009

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